EFM32HG108 Datasheet, PDF (34/53 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

Preliminary
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3.11 Voltage Comparator (VCMP)
Table 3.16. VCMP
Symbol
Parameter
Condition
Min
V_VCMPIN
V_VCMPCM
Input voltage range
VCMP Common
Mode voltage range
I_VCMP
Active current
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
t_VCMPREF
Startup time refer- NORMAL
ence generator
V_VCMPOFFSET Offset voltage
Single ended
Differential
V_VCMPHYST
VCMP hysteresis
t_VCMPSTART
Startup time
Typ
Max
V_DD
V_DD
0.2
Unit
V
V
µA
22
35 µA
10
µs
10
mV
10
mV
17
mV
10 µs
The V_DD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
V_{DD Trigger Level}=1.667V+0.034 ×TRIGLEVEL
3.12 I2C
Table 3.17. I2C Standard-mode (Sm)
(3.2)
Symbol
Parameter
Min
Typ
Max
Unit
f_SCL
SCL clock frequency
0
100¹ kHz
t_LOW
SCL clock low time
4.7
µs
t_HIGH
SCL clock high time
4.0
µs
t_SU,DAT
t_HD,DAT
SDA set-up time
SDA hold time
250
ns
8
3450^2,3 ns
t_SU,STA
Repeated START condition set-up time
4.7
µs
t_HD,STA
(Repeated) START condition hold time
4.0
µs
t_SU,STO
STOP condition set-up time
4.0
µs
t_BUF
Bus free time between a STOP and START condition
4.7
µs
1_{For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32HG Reference Manual.}
2_{The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).}
3_{When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10}-9 _{[s] * fHFPERCLK [Hz]) - 5).}
2015-05-06 - EFM32HG108FXX - _Rev0.91
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