EFM32TG840 Datasheet, PDF (53/70 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

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Alternate
LOCATION
Functionality 0
1
2
3
4
5
6
Description
US0_TX
PE10 PE7
PE13 PB7
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
PB7
PD2
PF0
USART1 clock input / output.
US1_CS
PB8
PD3
PF1
USART1 chip select input / output.
US1_RX
PD1
PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
US1_TX
PD0
PD7
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG840 is shown in Table 4.3 (p. 53) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Port A
Port B
Port C
Port D
Port E
Port F
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
PA15 PA14 PA13 PA12 -
-
-
-
-
PA6 PA5 PA4 PA3 PA2 PA1 PA0
- PB14 PB13 PB12 PB11 -
-
PB8 PB7 PB6 PB5 PB4 PB3
-
-
-
PC15 PC14 PC13 PC12 -
-
-
-
PC7 PC6 PC5 PC4
-
-
-
-
-
-
-
-
-
-
-
PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
4.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG840 is shown in Figure 4.2 (p. 54) .
2015-03-06 - EFM32TG840FXX - d0011_Rev1.40
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