EFM32TG840 Datasheet, PDF (35/70 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

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Symbol
Parameter
Condition
Min
SR_DAC
Sample rate
Continuous Mode
f_DAC
DAC clock frequen-
cy
Sample/Hold Mode
Sample/Off Mode
CYC_DACCONV Clock cyckles per
conversion
t_DACCONV
t_DACSETTLE
Conversion time
Settling time
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
SNR_DAC
Signal to Noise Ra-
tio (SNR)
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
500 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
500 kSamples/s, 12 bit, differ-
ential, V_DD reference
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
SNDR_DAC
Signal to Noise-
pulse Distortion Ra-
tio (SNDR)
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
500 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
500 kSamples/s, 12 bit, differ-
ential, V_DD reference
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
SFDR_DAC
Spurious-Free
Dynamic
Range(SFDR)
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
500 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
V_DACOFFSET Offset voltage
500 kSamples/s, 12 bit, differ-
ential, V_DD reference
After calibration, single ended
After calibration, differential
DNL_DAC
Differential non-lin- V_DD= 3.0 V, V_DD reference
earity
Typ
2
Max
Unit
500 ksam-
ples/s
1000 kHz
250 kHz
250 kHz
2
µs
5
µs
58
dB
59
dB
58
dB
58
dB
59
dB
57
dB
54
dB
56
dB
53
dB
55
dB
62
dBc
56
dBc
61
dBc
55
dBc
60
dBc
2
mV
2
mV
±1
LSB
2015-03-06 - EFM32TG840FXX - d0011_Rev1.40
35
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