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Table 3.20. EBI Write Enable Timing
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Symbol
Parameter
Min
Typ Max Unit
t_{OH_WEn} ^{1 2 3 4}
Output hold time, from trailing EBI_WEn/
-6.00 + (WRHOLD *
ns
EBI_NANDWEn edge to EBI_AD, EBI_A,
t_HFCORECLK)
EBI_CSn, EBI_BLn invalid
t_{OSU_WEn} ^{1 2 3 4 5}
Output setup time, from EBI_AD, EBI_A,
-14.00 + (WRSETUP
ns
EBI_CSn, EBI_BLn valid to leading EBI_WEn/
* t_HFCORECLK)
EBI_NANDWEn edge
t_{WIDTH_WEn} ^{1 2 3 4 5} EBI_WEn/EBI_NANDWEn pulse width
-7.00 + ((WRSTRB
ns
+1) * t_HFCORECLK)
1_{Applies for all addressing modes (figure only shows D16 addressing mode)}
2_{Applies for both EBI_WEn and EBI_NANWEn (figure only shows EBI_WEn)}
3_{Applies for all polarities (figure only shows active low signals)}
4_{Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)}
5 _{The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFWE=0. The leading edge}
of EBI_WEn can be moved to the right by setting HALFWE=1. This decreases the length of t_{WIDTH_WEn} and increases the length
of t_{OSU_WEn} by 1/2 * t_HFCLKNODIV.
Figure 3.39. EBI Address Latch Enable Related Output Timing
EBI_AD[ 1 5 : 0 ]
EBI_ALE
EBI_CSn
EBI_WEn
ADDRSETUP
(1, 2, 3, ...)
ADDR[ 1 6 : 1 ]
t WIDTH_ALEn
t OSU_ALEn
ADDRHOLD
(0, 1, 2, ...)
t WIDTH_ALEn
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
DATA[15:0]
WRHOLD
(0, 1, 2, ...)
Z
Table 3.21. EBI Address Latch Enable Related Output Timing
Symbol
Parameter
Min
Typ Max Unit
t_{OH_ALEn} ^{1 2 3 4}
Output hold time, from trailing EBI_ALE edge to
EBI_AD invalid
-6.00 + (AD-
DRHOLD⁵ * t_HFCORE-
ns
CLK⁾
t_{OSU_ALEn} ^{1 2 4}
Output setup time, from EBI_AD valid to leading
-13.00 + (0 * t_HFCORE-
ns
EBI_ALE edge
CLK⁾
t_{WIDTH_ALEn} ^{1 2 3 4} EBI_ALEn pulse width
-7.00 + (ADDRSET-
ns
UP+1) * t_HFCORECLK)
1_{Applies to addressing modes D8A24ALE and D16A16ALE (figure only shows D16A16ALE)}
2_{Applies for all polarities (figure only shows active low signals)}
3 _{The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge}
of EBI_ALE can be moved to the left by setting HALFALE=1. This decreases the length of t_{WIDTH_ALEn} and increases the length
of tOH_ALEn by t_HFCORECLK - 1/2 * t_HFCLKNODIV.
4_{Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)}
5_{Figure only shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state}
instead of via the ADDRHOLD state.
2014-06-13 - EFM32WG395FXX - d0194_Rev1.40
50
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