SI88X4X Datasheet, PDF (5/48 Pages) Silicon Laboratories – Precise timing on digital isolators

Si88x4x
Table 2. Electrical Characteristics¹ (Continued)
V_IN = 24 V; V_DDA = 4.3 V (see Figure 3) for all Si8844x/64x; V_DDA = V_DDP = 3.0 to 5.5 V (see Figure 2) for all Si8824x/34x;
T_A = –40 to 125 °C unless otherwise noted
Parameter
No Load Supply Current
IDDP
Si8844x, Si8864x
No Load Supply Current
IDDA
Si8844x, Si8864x
Symbol
IDDPQ_DCDC³
IDDAQ_DCDC⁴
Test Condition
See Figure 3
VIN = 24 V
See Figure 3
VIN = 24 V
Min Typ Max Unit
—
0.8
—
mA
—
5.8
—
mA
Peak Efficiency
Si8824x, Si8834x
Si8844x, Si8864x

See Figure 2, 3
—
—
%
78
83
Voltage Regulator Refer-
ence Voltage
Si8844x, Si8864x
VREGA,
I_REG = 600 μA
—
4.8
—
V
VREGB
See Figure 30 for typical I–V
curve
VREG tempco
K_TVREG
— –0.43 — mV/°C
VREG input current
I_REG
350
—
950
μA
Soft Start Time, Full Load
Si8824x, Si8844x
Si8834x, Si8864x
t_SST
See Figures 25 through 28 for —
—
ms
typical soft start times over
25
load conditions.
50
Restart Delay from fault
event
tOTP
—
21
—
s
Digital Isolator
VDD Undervoltage
Threshold
VDDUV+
VDDA, VDDB rising
—
2.7
—
V
VDD Undervoltage
Threshold
VDDUV–
VDDA, VDDB falling
—
2.6
—
V
VDD Undervoltage
Hysteresis
VDD_HYS
— 100 —
mV
Positive-Going Input
VT+
All inputs rising
— 1.67 —
V
Threshold
Notes:
1. Over recommended operating conditions as noted in Table 1.
2. VOUT = VSNS x (1 + R1/R2) + R1 x I_offset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
Preliminary Rev. 0.6
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