SI52111-B5 Datasheet, PDF (5/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR

Si52111-B5/B6
Table 3. AC Electrical Specifications (Continued)
Parameter
Cycle-to-Cycle Jitter
PCIe Gen 1 Pk-Pk Jitter,
Common Clock
PCIe Gen 2 Phase Jitter,
Common Clock
PCIe Gen 3 Phase Jitter,
Common Clock
Symbol
T_CCJ
Pk-Pk_GEN1
RMS_GEN2
RMS_GEN3
Test Condition
Measured at 0 V differential
PCIe Gen 1
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
PCIe Gen 3 Phase Jitter,
Separate Reference No Spread,
SRNS
PCIe Gen 4 Phase Jitter,
Common Clock
RMS_{GEN3_SRNS}
RMS_GEN4
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
Crossing Point Voltage at 0.7 V
Swing
Voltage High
Voltage Low
Spread Range
Modulation Frequency
V_OX
V_HIGH
V_LOW
S_RNG
F_MOD
Down Spread, -B6 only
-B6 only
Enable/Disable and Set-up
Clock Stabilization from
Power-up
Stopclock Set-up Time
T_STABLE
T_SS
Notes:
1. Visit www.pcisig.com for complete PCIe specifications.
2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5
3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Min
—
—
—
—
—
—
—
300
—
–0.3
—
30
—
10.0
Typ
28
24
1.35
1.4
0.4
0.28
0.4
—
—
—
–0.5
31.5
—
—
Max Unit
70
ps
86
ps
3.0
ps
3.1
ps
1.0
ps
0.71 ps
1.0
ps
550 mV
1.15
V
—
V
—
%
33
kHz
3
ms
—
ns
Rev 1.2
5