ISL15100 Datasheet, PDF (5/9 Pages) Intersil Corporation – Single differential driver

ISL15100
Electrical Specifications V_S+ = +12V, V_S- = GND = 0V, see Figure 3, Full Bias (C₀ = C₁ = 0V), T_A = +25°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNIT
Inverting Input Bias Current Mismatch I_B-DM
Difference between the INA- and INB- input -35
0
35
µA
bias currents
Inverting Input Bias Current Common
Mode
I_B-CM
Average inverting input bias currents
(Note 7)
-90
-30
55
µA
Input Offset Voltage
V_IOA, V_IOB
Voltage difference from INA+ to INA- and
-85
0
85
mV
from INB+ to INB-
Input Offset Voltage Mismatch
Input Offset Voltage Common Mode
V_IODM
V_IOCM
V_IOA - V_IOB
Average offset voltage across the two
inputs
-5
0
5
mV
-80
20
80
mV
Differential Mode Output Offset Voltage V_OSDM
Output referred total effect of all
differential DC error terms
-7.8
0
7.8
mV
Common Mode Output Offset Voltage V_OSCM
Output referred total effect of all common -105
40
145
mV
mode DC errors
Input Headroom to Positive Supply
(V_S+) - V_IN(MAX)
INA+ and INB+ required margin to V_S+
supply
3
V
Input Headroom to Negative Supply
V_IN(MIN) - (V_S-)
INA+ and INB+ required margin to V_S-
supply
3
V
OUTPUT CHARACTERISTICS
Output Swing
V_O-OPEN
V_S = ±6V, Differential R_LOAD ≥ 1kΩ, each ±4.85 ±5.0
V
output pin voltage range
V_O-LOADED
V_S = ±6V, V_O in linear region, Differential
±4.6
V
R_LOAD = 29Ω, each output pin voltage
range.
V_S = ±6V, V_O driven into the rail, differential ±4.2
±4.7
V
R_LOAD = 29Ω, each output pin voltage
range.
Output Current
POWER SUPPLY
I_O
Linear output current (not short circuit)
±300 ±400
mA
Bipolar Supply Range
±V_S
Symmetric supply, pin 4 at GND for logic
±4
±6
±6.6
V
reference
Single Supply Range
V_S+
Single supply with V_S- and pin 4 at GND
8
12
13.2
V
Positive Supply Currents
I_S+ (Full bias)
V_O(DIFF) = 0V, C₀ = C₁ = 0V
27
32
37
mA
I_S+ (Medium bias) V_O(DIFF) = 0V, C₀ = 3.3V, C₁ = 0V
19
23
26
mA
I_S+ (Low bias)
V_O(DIFF) = 0V, C₀ = 0V, C₁ = 3.3V
12
15
18
mA
I_S+ (Power down) C₀ = C₁ = 3.3V
5.5
7
8.5
mA
C₀, C₁ Input High Current
I_INH, C₀ or C₁
C₀ = C₁ = 3.3V (Note 7)
-150
-90
-30
µA
C₀, C₁ Input Low Current
I_INL, C₀ or C₁
C₀ = C₁ = 0V (Note 7)
-1.5
1
1.5
µA
C₀, C₁ Logic High Voltage
V_INH
Pin 4 at GND, logic reference pin
2
3.3
5.5
V
C₀, C₁ Logic Low Voltage
V_INL
Pin 4 at GND, logic reference pin
-0.3
0
0.8
V
NOTES:
6. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
7. Positive currents flow out of the pin.
5
FN8577.0
September 19, 2013