EFM32TG825 Datasheet, PDF (47/67 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

BGA48 Pin#
and Name
Pin Name
Analog
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Pin Alternate Functionality / Description
Timers
Communication
Other
A3
PE11
LCD_SEG7
TIM1_CC1 #1
US0_RX #0
LES_ALTEX5 #0
BOOT_RX
A4
PF5
LCD_SEG3
PRS_CH2 #1
A5
PF3
LCD_SEG1
PRS_CH0 #1
A6
PC14
ACMP1_CH6
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
LES_CH14 #0
A7
PC15
ACMP1_CH7
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
LES_CH15 #0
DBG_SWO #1
B1
PA1
LCD_SEG14
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
B2
PA0
LCD_SEG13
TIM0_CC0 #0/1/4
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
B3
PE10
LCD_SEG6
TIM1_CC0 #1
US0_TX #0
BOOT_TX
B4
PF4
LCD_SEG2
PRS_CH1 #1
B5
PF2
LCD_SEG0
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
B6
PE7
LCD_COM3
US0_TX #1
B7
PC13
ACMP1_CH5
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
LES_CH13 #0
C1
PB3
LCD_SEG20/
LCD_COM4
C2
PA2
LCD_SEG15
TIM0_CC2 #0/1
CMU_CLK0 #0
C3
VSS
Ground.
C4
IOVDD_5
Digital IO power supply 5.
C5
PF1
TIM0_CC1 #5
LETIM0_OUT1 #2
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
DBG_SWDIO #0/1
GPIO_EM4WU3
C6
PE5
LCD_COM1
US0_CLK #1
C7
PE6
LCD_COM2
US0_RX #1
D1
PB4
LCD_SEG21/
LCD_COM5
D2
PB6
LCD_SEG23/
LCD_COM7
D3
IOVDD_0
Digital IO power supply 0.
D5
PF0
TIM0_CC0 #5
LETIM0_OUT0 #2
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
DBG_SWCLK #0/1
D6
PE4
LCD_COM0
US0_CS #1
D7
DECOUPLE
Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLE is required at this pin.
E1
PB5
LCD_SEG22/
LCD_COM6
E2
PC4
ACMP0_CH4
DAC0_P0 /
OPAMP_P0
LETIM0_OUT0 #3
LES_CH4 #0
E3
PA12
LCD_BCAP_P
2015-03-06 - EFM32TG825FXX - d0206_Rev1.40
47
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