SI5040-EVB Datasheet, PDF (4/24 Pages) Silicon Laboratories – Four selectable on-chip reference frequencies

Si5040-EVB
1.3.1. MCU to Si5040 Serial Communications
(Status and Control)
The microcode within the MCU is designed to
communicate with the Si5040 when SPSEL pin 9 is high
(JP11 no jumper). In this mode, the serial data transfer
from the MCU to the Si5040 is very similar to the SPI
protocol but with a single bidirectional data line rather
than two unidirectional data lines. However, one could
write new microcode for the MCU that uses the SMBus
(I²C compatible) to communicate with the Si5040. To
enable SMBus communication between the Si5040 and
the MCU, you must install a jumper on JP11 and on J17
between SD/SMB_DAT, SCK/SMB_CK and SS/SS_U.
See Figure 4. Note that INTRPT on JP17 should be
labeled as INTRPTB because the interrupt from the
Si5040 is an active low signal.
Figure 5. External MCU
1.3.3. Reference Clock
To use the on-chip reference clock (Si534), JP16 must
be set to the ON position. When this is done, the REF
ON LED will light, indicating that power is applied to the
Si534. The output frequency of the Si534 is controlled
by jumpers JP17 and JP18 (see Figure 6).
Figure 4. SMBus Protocol
1.3.2. External MCU Control
To use an external MCU, make sure that all jumpers are
removed from J17 and that JP11 does not have a
jumper (see Figure 5). Now, the following pins of J17
are available for connection to an external MCU.
 SCK
 SD
 SS
 RXLOS
 RXLOL
 INTRPT
 SPSEL
 GND
The Silicon Labs MCU that is well-suited for use within
XFP Modules is the C8051F330.
Figure 6. Reference Clock
1.3.4. Synchronous Test Clock
By setting Register 57 to 9Ch, the Tx CMU clock divided
by 64 will be output at J2 and J3. The EVB must have
jumpers on JP2 and JP3 to enable the /64 clock output
(see Figure 7). By setting Register 57 to 1Ch, the Rx
CMU clock divided by 64 will be output at J2 and J3.
When jumpers are placed on JP2 and JP3, the
functionality of RXLOS and RXLOL is lost, and the state
of the LEDs for these two signals becomes invalid. To
return the RXLOL and RXLOS signals to their normal
modes, set Register 57 to 00h, and remove the jumpers
on JP2 and JP3. Register 57 cannot be changed with
the System Programmer GUI, you must use the
Register Programmer GUI (see page 8).
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Rev. 0.4