SI5013-EVB Datasheet, PDF (4/11 Pages) Silicon Laboratories – Differential I/Os ac coupled

Si5013-EVB
RMS and peak-to-peak jitter on the CDR CLKOUT.
Thus, any jitter measured is jitter generated by the
CDR.
Jitter Transfer: Referring to Figure 3, this test requires a
pattern generator, a clock source (synthesizer signal
source), a modulation source, a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50 ). During this test, the Jitter
Analyzer modulates the data pattern and data clock
reference. The modulated data clock reference is
compared with the CLKOUT of the CDR. Jitter on
CLKOUT relative to the jitter on the data clock reference
is plotted versus modulation frequency at predefined
jitter amplitudes.
Pulse
Generator
Scope
DATAOUT– _Pattern GPIB
Analyzer
3.3 V
+–
REFCLK+
+ _REFCLK
– _(optional)
REFCLK–
+
DATAOUT _–
DATAOUT+
DATAIN+
DATAIN–
+
–
DATAIN
CLKOUT
+
–
Si5013-EVB
CLKOUT+
CLKOUT–
Pattern ^{Data Clock+}
Generator
Jitter
Analyzer
GPIB
Synthesizer
Modulation ^GPIB
Clock _{Signal Source FM}
Source
GPIB
Figure 3. Test Configuration for Jitter Tolerance, Transfer, and Generation
4
Rev. 1.0