SI530 Datasheet, PDF (3/10 Pages) Silicon Laboratories – CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)

Si530/531
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option¹
LVDS Output Option²
CML Output Option²
CMOS Output Option³
Rise/Fall time (20/80%)
Symbol
V_O
V_OD
V_SE
V_O
V_OD
V_O
V_OD
V_OH
V_OL
t_R, t_F
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
mid-level
swing (diff)
I_OH = 32 mA
I_OL = 32 mA
LVPECL/LVDS/CML
CMOS with CL = 15 pF
Min
Typ
Max Units
V_DD – 1.42
1.1
0.5
1.125
—
—
—
1.20
V_DD – 1.25 V
1.9
V_PP
0.93
V_PP
1.275
V
0.32
0.40
0.50
V_PP
—
V_DD – 0.75
—
V
0.70
0.95
1.20
V_PP
0.8 x V_DD
—
—
—
V_DD
V
0.4
—
—
350
ps
—
1
—
ns
Symmetry (duty cycle)
SYM LVPECL: V_DD – 1.3 V (diff)
LVDS: 1.25 V (diff)
45
—
55
%
CMOS: V_DD/2
Notes:
1. 50 Ω to V_DD – 2.0 V.
2. R_term = 100 Ω (differential).
3. C_L = 15 pF
Table 4. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Phase Jitter (RMS)*
for F_OUT > 500 MHz
φ_J
12 kHz to 20 MHz (OC-48)
—
50 kHz to 80 MHz (OC-192)
—
Phase Jitter (RMS)*
for F_OUT of 125 to 500 MHz
φ_J
12 kHz to 20 MHz (OC-48)
—
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Typ
0.27
0.30
0.50
Max Units
—
ps
—
—
ps
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Period Jitter*
for F_OUT < 160 MHz
J_PER
RMS
Peak-to-Peak
—
1
—
ps
—
5
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Preliminary Rev. 0.4
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