SI530 Datasheet, PDF (1/10 Pages) Silicon Laboratories – CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)

Si530/531
PRELIMINARY DATA SHEET
CRYSTAL OSCILLATOR (XO)
(10 MHZ TO 1.4 GHZ)
Features
„ Available with any-rate output
„ Internal fixed crystal frequency
frequencies from 10 MHz to 945 MHz ensures high reliability and low
and select frequencies to 1.4 GHz
aging
„ 3rd generation DSPLL^® with superior ^{„ Available CMOS, LVPECL,}
jitter performance
LVDS, and CML outputs
„ 3x better frequency stability than ^{„ 3.3, 2.5, and 1.8 V supply options}
SAW-based oscillators
„ Industry-standard 5 x 7 mm
package and pinout
„ Pb-free/RoHS-compliant
Applications
Si5602
Ordering Information:
See page 6.
„ SONET/SDH
„ Networking
„ SD/HD video
„ Clock and data recovery
„ FPGA/ASIC clock generation
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL^® circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Functional Block Diagram
Pin Assignments:
See page 5.
(Top View)
NC 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si530 (LVDS/LVPECL/CML)
OE 1
NC 2
6 VDD
5 NC
GND 3
4 CLK+
V_DD
CLK– CLK+
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
OE
GND
OE 1
6 VDD
NC 2
5 CLK–
GND 3
4 CLK+
Si531 (LVDS/LVPECL/CML)
Preliminary Rev. 0.4 5/06
Copyright © 2006 by Silicon Laboratories
Si530/531
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.