SI5020-EVB Datasheet, PDF (3/12 Pages) Silicon Laboratories – Simple jumper configuration

Si5020-EVB
RATESEL1
RATESEL0
PWRDN/
CAL
2488 Mbps
RATESEL1
RATESEL0
PWRDN/
CAL
1244 Mbps
RATESEL1
RATESEL1
RATESEL0
RATESEL0
PWRDN/
CAL
622 Mbps
PWRDN/
CAL
155 Mbps
Figure 1. RATESEL Jumper Configurations
Loss-of-Lock (LOL)
LOL is an indicator of the relative frequency between
the data and the REFCLK. LOL will assert when the
frequency difference is greater than ±600 PPM. In order
to prevent LOL from de-asserting prematurely, there is
hysterisis in returning from the out-of-lock condition.
LOL will be de-asserted when the frequency difference
is less than ±300 PPM.
LOL is wired to a test point which is located on the
upper right-hand side of the evaluation board.
Jitter Generation: Referring to Figure 2, this test
requires a pattern generator, a clock source
(synthesizer signal source), a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50 ). During this test, there is no
modulation of the Data Clock, so the data that is sent to
the CDR is jitter free. The Jitter Analyzer measures the
RMS and peak-to-peak jitter on the CDR CLKOUT.
Thus, any jitter measured is jitter generated by the
CDR.
Jitter Transfer: Referring to Figure 2, this test requires
a pattern generator, a clock source (synthesizer signal
source), a modulation source, a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50 ). During this test the Jitter
Analyzer modulates the data pattern and data clock
reference. The modulated data clock reference is
compared with the CLKOUT of the CDR. Jitter on
CLKOUT relative to the jitter on the data clock reference
is plotted versus modulation frequency at predefined
jitter amplitudes.
Test Configuration
The three critical tests that are typically performed on a
CDR device are jitter transfer, jitter tolerance, and jitter
generation. By connecting the Si5020 Evaluation Board
as shown in Figure 2, all three measurements can be
easily made.
REFCLK should be within ±100 PPM of the frequency
selected from Table 1. RATESEL must be configured to
match the desired data rate, and PWRDN/CAL must be
unjumpered.
Jitter Tolerance: Referring to Figure 2, this test
requires a pattern generator, a clock source
(synthesizer signal source), a modulation source, a jitter
analyzer, a pattern analyzer, and a pulse generator (all
unconnected high-speed outputs must be terminated to
50 ). During this test the Jitter Analyzer causes a
modulation on the data pattern which drives the DATAIN
ports of the CDR. The Bit-Error-Rate (BER) is monitored
on the Pattern Analyzer. The modulation (jitter)
frequency and amplitude is recorded when the BER
approaches a specified threshold.
Rev. 1.0
3