SI5020-EVB Datasheet, PDF (1/12 Pages) Silicon Laboratories – Simple jumper configuration

Si5020-EVB
EVALUATION BOARD FOR Si5020 SiPHY™ MULTI-RATE
SONET/SDH CLOCK AND DATA RECOVERY IC
Description
Features
The Si5020 evaluation board provides a platform for
testing and characterizing Silicon Laboratories’ Si5020
SiPHY™ multi-rate SONET/SDH clock and data
recovery IC. The Si5020 CDR supports OC-48/12/3,
STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC rates.
All high-speed I/Os are AC coupled to ease interfacing
to industry standard test equipment.
 Single 2.5 V power supply
 Differential I/Os ac coupled
 Simple jumper configuration
Function Block Diagram
Pulse
Generator
Pattern
Generator
Z_C = 50 
Z_C = 50 
Z_C = 50 
Z_C = 50 
+
REFCLK
–
+
CLKOUT
–
Si5020
+
DATAIN
–
+
DATAOUT
–
RATESEL0
RATESEL1
PWRDN/CAL
LOL
REXT
Jumpers
Si5020-EVB
Rev C
Z_C = 50 
Z_C = 50 
Z_C = 50 
Z_C = 50 
Jitter
Analyzer
Scope
Pattern
Analyzer
10 k
Test
Point
Rev. 1.0 12/02
Copyright © 2016 by Silicon Laboratories
Si5020-EVB-10