SI4420 Datasheet, PDF (27/33 Pages) Silicon Laboratories – No alignment required in production

Sensitive Reset Enabled, Ripple on Vdd:
Si4420
Vdd
1.6V
H
nRes
output
L
Reset threshold voltage
(600mV)
Reset ramp line
(100mV/ms)
time
Sensitive reset disabled:
Vdd
250mV
H
nRes
output
L
Reset threshold voltage
(600mV)
Reset ramp line
(100mV/ms)
time
Hardware reset
The hardware reset puts the controller and the corresponding analog circuits into their default state and loads the power-on values of the
registers. This mode can be activated by pulling the nRES input (pin 10) to logic low for at least 1us. The chip is ready for operation 1ms after
releasing (setting to logic H) the nRES pin.
Software reset
Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The result of the
command is the same as if power-on reset was occurred. When the nRES pin connected to the reset pin of the microcontroller, using the
software reset command may cause unexpected problems.
Vdd line filtering
During the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to keep
the Vdd line as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out from
reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing signal below
10mVp-p in the DC – 50kHz range for 200ms from Vdd ramp start.. Typical example when a switch-mode regulator is used to supply the radio,
switching noise may be present on the Vdd line. Follow the manufacturer’s recommendations how to decrease the ripple of the regulator IC
and/or how to shift the switching frequency.
Related control commands
“FIFO and Reset Mode Command”
Setting bit<0> to high will change the reset mode to normal from the default sensitive.
“SW Reset Command”
Issuing FE00h command will trigger software reset. See the Wake-up Timer Command.
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