SI4420 Datasheet, PDF (23/33 Pages) Silicon Laboratories – No alignment required in production

Si4420
TX REGISTER BUFFERED DATA TRANSMISSION
In this operating mode (enabled by bit el, the Configuration Control Command) the TX data is clocked into one of the two 8-bit data registers.
The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management
Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored
to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller.
TX Register Simplified Block Diagram (Before Transmit)
et=0
(register initial
fillup)
Di
8 bit shift register
(default: AAh) ^Do
CLK
TX_DATA
Serial bus data
Serial bus clk
Di
8 bit shift register
(default: AAh)
Do
CLK
TX Register Simplified Block Diagram (During Transmit)
et=1
(during TX)
Bit rate
1:8
divider
Serial bus
clk
Serial bus
data
SEL
Y
I0
I1
MUX
Di _{8 bit shift register Do}
CLK
SEL
Y
I0
I1
MUX
TX_DATA
Di _{8 bit shift register Do}
SEL
Y
I0
CLK
I1
MUX
Typical TX Register Usage
SPI commands
(nSEL, SCK, SDI)
et bit
(enable transmitter)
Conf. cnt.
el=1
TX latch wr TX latch wr
TX byte1 TX byte2
enable
Synthesizer / PA
TX data
Power Man
et=1
TX latch wr TX latch wr
TX byte3 Dummy
TX byte
Power Man
et=0
Synt.
tsp*
PA
80u
s
TX byte1 TX byte2 TX byte3 Dummy byte
nIRQ
SDO**
Note:
*tsp is the start-up time of the PLL
** SDO is tri-state if nSEL is logic high.
Note: The content of the data registers are initialized by clearing bit et.
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