SI1010 Datasheet, PDF (267/384 Pages) Silicon Laboratories – Ultra Low Power, 16/8 kB, 12/10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver

Si1010/1/2/3/4/5
23.5.4. ADC
The amplified IQ IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low
current consumption and high dynamic range. The bandpass response of the ADC provides exceptional
rejection of out of band blockers.
23.5.5. Digital Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed
in the digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the
following functions:
 Channel selection filter
 TX modulation
 RX demodulation
 AGC
 Preamble detector
 Invalid preamble detector
 Radio signal strength indicator (RSSI)
 Automatic frequency compensation (AFC)
 Packet handling including EZMAC^® features
 Cyclic redundancy check (CRC)
The digital channel filter and demodulator are optimized for ultra low power consumption and are highly
configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured
to support bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported
ranging from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control
loop optimized for fast response time.
The configurable preamble detector is used to improve the reliability of the sync-word detection. The sync-
word detector is only enabled when a valid preamble is detected, significantly reducing the probability of
false detection.
The received signal strength indicator (RSSI) provides a measure of the signal strength received on the
tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel
power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT)
functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital auto-
matic frequency control (AFC) in receive mode.
A comprehensive programmable packet handler including key features of Silicon Labs’ EZMAC is inte-
grated to create a variety of communication topologies ranging from peer-to-peer networks to mesh net-
works. The extensive programmability of the packet header allows for advanced packet filtering which in
turn enables a mix of broadcast, group, and point-to-point communication.
A wireless communication channel can be corrupted by noise and interference, and it is therefore impor-
tant to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the
presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmit-
ted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and
CRC can significantly reduce the load on the microcontroller reducing the overall current consumption.
The digital modem includes the TX modulator which converts the TX data bits into the corresponding
stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator.
This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter
is implemented to support GFSK, considerably reducing the energy in the adjacent channels. The default
bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to other values.
Rev. 1.0
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