SI1010 Datasheet, PDF (123/384 Pages) Silicon Laboratories – Ultra Low Power, 16/8 kB, 12/10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver

Si1010/1/2/3/4/5
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
Si1010/1/2/3/4/5 device family is shown in Figure 9.1
PROGRAM/DATA MEMORY
(FLASH)
0x01FF
0x0000
0x3FFF
0x3C00
0x3BFF
Si1010/2/4
Scrachpad Memory
(DATA only)
RESERVED
16KB FLASH
0x0000
(In-System
Programmable in 512
Byte Sectors)
0x01FF
0x0000
0x1FFF
Si1011/3/5
Scrachpad Memory
(DATA only)
8KB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
DATA MEMORY
(RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing Only)
Special Function
Registers
(Direct Addressing Only)
0
F
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
0x1FFF
Unpopulated Address Space
0x0200
0x01FF
0x0000
XRAM - 512 Bytes
(accessable using MOVX
instruction)
Figure 9.1. Si1010/1/2/3/4/5 Memory Map
9.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The Si1010/1/2/3/4/5 devices implement 16 kB
(Si1010/2/4) or 8 kB (Si1011/3/5) of this program memory space as in-system, re-programmable Flash
memory, organized in a contiguous block from addresses 0x0000 to 0x3BFF (Si1010/2/4) or 0x1FFF
(Si1011/3/5). The last byte of this contiguous block of addresses serves as the security lock byte for the
device. Any addresses above the lock byte are reserved.
Rev. 1.0
123