ISL1801 Datasheet, PDF(22/30 Page) Intersil Corporation – sPMIC for Micro Converter Bias and Drivers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ISL1801 Datasheet, PDF (22/30 Pages) Intersil Corporation – sPMIC for Micro Converter Bias and Drivers

◁

ISL1801

t15: WDI voltage changes from VDDREF to 0.6*VDDREF; Since

it does not cross the VDDREF/2 threshold no falling edge

signal is generated; TIMER continues ramping up.

t16: TIMER is not reset in time, and reaches the 90% threshold

level; PGOOD2 is pulled low for 1ms to reset MCU; and

TIMER is reset for 1.5ms.

t17: PGOOD2 goes back high to exit MCU reset; then TIMER

ramps up.

t18: TIMER is reset for 1.5ms by the WDI falling edge; then

TIMER ramps up.

t19: TIMER is reset by the WDI rising edge; WDI is above

90%*VCC5V threshold level, watchdog function is disabled.

TIMER ramps up and stays at its high state however it does

not trigger a time-out.

t20: WDI drops below the 90%*VCC5V threshold level,

watch-dog function is enabled; TIMER is reset for 1.5ms by

the WDI falling edge; then TIMER ramps up.

VIN1

PWM1

FB1

PVCC3

Vth2Vth3

VR1 current

limiting level

PRELOAD

Current

TIMER

VCC5V

4.5V

OFF

POR

PWM2

Vout2

PGOOD2

OPAMP,

COMPARATORS,

DRIVER3,

BDRIVE

Disabled

Enabled

PWM3

t0 t1 t2

t3 t4 t5 t6

t7 t8 t9

t10

FIGURE 26. POWER-UP SEQUENCE

Power-Up Sequence

Before t0, the PV module does not output any voltage

t0: Panel output voltage VIN1 starts to ramp up; LDO1 is ON to

pull VOUT1 (=PVCC3) up; LDO2 runs in saturated condition

to pull VCC5V up.

t1: When VCC5V reaches its power on reset (POR) level (4.5V),

the ISL1801 starts to operate and monitor the voltage at the

TIMER pin; after TIMER reaches its threshold (90% * VCC5),

the ISL1801 starts to initialize all internal circuits; then VR1

starts to run at the maximum duty cycle, and the VR1 current

limiting level starts to ramp up step-by-step; LDO1 continues

to output some current until PVCC3 reaches about 6.2V.

t2: VR1 current limiting level ramps up to its final value.

t3: FB1 reaches Vth3 (90% of its final value), the preload

switches are turned on in sequence to apply the preload

current to the VR1 output.

t4: If the PV module does not have sufficient output power,

PVCC3 will drop to Vth2 (fixed at 7V) when the preload is

applied; this triggers the immediate removal of all preload

current followed by a 500Âµs delay.

Submit Document Feedback 22

FN8259.1

July 24, 2014

▷