SI5310-EVB Datasheet, PDF (2/12 Pages) Silicon Laboratories – Simple jumper configuration

Si5310-EVB
Functional Description
The evaluation board simplifies characterization of the
Si5310 precision clock multiplier/regenerator IC by
providing access to all of the Si5310 I/Os. Device
performance can be evaluated by following the “Test
Configuration” section. Specific performance metrics
include jitter tolerance, jitter generation, and jitter
transfer.
Power supply
The evaluation board requires one 2.5 V supply. Supply
filtering is placed on the board to filter typical system
noise components; however, initial performance testing
should use a linear supply capable of supplying 2.5 V
±5% DC.
CAUTION: The evaluation board is designed so that the
body of the SMA jacks and GND are shorted. Care must
be taken when powering the PCB at potentials other
than GND at 0.0 V and VDD at 2.5 V relative to chassis
GND.
Self-Calibration
The Si5310 device provides an internal self-calibration
function that optimizes the loop gain parameters within
the internal DSPLL^TM. Self-calibration is initiated by a
high-to-low transition of the PWRDN/CAL signal while a
valid reference clock is supplied to the REFCLK input.
On the Si5310-EVB board, a voltage detector IC is
utilized to initiate self-calibration. The voltage detector
drives the PWRDN/CAL signal low after the supply
voltage has reached a specific voltage level. This circuit
is described in Silicon Laboratories application note
AN42. On the Si5310-EVB, the PWRDN/CAL signal is
also accessible via a jumper located in the lower left-
hand corner of the evaluation board. PWRDN/CAL is
wired to the center post (signal post) between 2.5 V and
GND.
Device Power Down
The Si5310 device can be powered down via the
PWRDN/CAL signal. When PWRDN/CAL is driven high
(2.5 V) the evaluation board will draw minimal current.
On the Si5310-EVB board, the PWRDN/CAL signal may
be controlled via a jumper located in the lower left-hand
corner of the evaluation board. PWRDN/CAL is wired to
the center post (signal post) between 2.5 V and GND.
CLKIN, CLKOUT, MULTOUT
These high-speed I/Os are wired to the board perimeter
on 30 mil (0.030 inch) 50  microstrip lines to the end-
launch SMA jacks as labeled on the PCB. These I/Os
are AC coupled to simplify direct connection to a wide
array of standard test hardware. Because each of these
signals are differential both the positive (+) and negative
(–) terminals must be terminated to 50 . Terminating
only one side will degrade the performance of the
Si5310 device. The CLKIN inputs are terminated on the
die with 50  resistors.
Note: The 50  termination is for each terminal/side of a dif-
ferential signal, thus the differential termination is actu-
ally 50  + 50  = 100 .
REFCLK
REFCLK is used to center the frequency of the Si5310
DSPLL so that the device can lock to the CLKIN signal.
For a given CLKIN rate, there are five choices for the
REFCLK frequency. These five options are all multiples
of the CLKIN frequency, as indicated in Table 1. The
REFCLK frequency is automatically detected by the
Si5310 device, so no digital control inputs are needed
for REFCLK frequency selection. REFCLK may be
synchronous or asynchronous with respect to CLKIN.
However, REFCLK must be within ±100 PPM of the
target CLKIN frequency multiple. REFCLK is ac coupled
to the SMA jacks located on the top side of the
evaluation board. The REFCLK inputs are terminated
on the die with 50  resistors.
Note: The 50  termination is for each terminal/side of a dif-
ferential signal, thus the differential termination is actu-
ally 50  + 50  = 100 .
MULTSEL
MULTSEL is a binary input to the Si5310 device that
selects the frequency range for the MULTOUT clock
output. The MULTOUT output frequency is a multiple of
the CLKIN input frequency. The frequency for
MULTOUT will be in either the 150–167 MHz frequency
range or the 600–668 MHz frequency range depending
on the state of the MULTSEL signal as indicated in
Table 1. On the Si5310 evaluation board, MULTSEL is
controlled via a jumper located in the lower left-hand
corner of the board. MULTSEL is wired to the center
post (signal post) between 2.5 V and GND.
The jumper configurations for MULTSEL are indicated
in Figure 1.
2
Rev. 0.71