SI52144-EVB Datasheet, PDF (2/6 Pages) Silicon Laboratories – Power consumption test

Si52144-EVB
1. Front Panel
External Clock Input for
Si52144-EVB only
3.3 V Power Supply Connector
GND Connector
VDD Connectors
OE1 Hardware Input
Control for DIFF1 Output
SSON Spread Select Input
OE2 Hardware Input
Control for DIFF2 Output
OE0 Hardware Input
Control for DIFF0 Output
Si52144 Device Mount
I²C Connect for I²C Read and
Write. In sequence SData,
GND, SCLK from left to right.
OE_DIFF3 Hardware Input
Control for DIFF3 Output
DIFF3 Differential Output
DIFF2 Differential Output
DIFF1 Differential Output
DIFF0 Differential Output
Jumper Label
OE0
OE1
OE2
OE3
SSON
SDATA
SCLK
Figure 1. Evaluation Module Front Panel
Table 1. Input Jumper Settings
Type
Description
I OE0, 3.3 V Input for Enabling DIFF0 Clock Output.
1 = DIFF0 enabled, 0 = DIFF0 disabled.
I _{OE1, 3.3 V Input for Enabling DIFF1 Clock Output.}
1 = DIFF1 enabled, 0 = DIFF1 disabled.
I OE2, 3.3 V Input for Enabling DIFF2 Clock Output.
1 = DIFF2 enabled, 0 = DIFF2 disabled.
I _{OE3, 3.3 V Input for Enabling DIFF3 Clock Output.}
1 = DIFF3 enabled, 0 = DIFF3 disabled.
I _{SSON Input, 3.3 V-Tolerant Active Input for Spread Selection.}
Internal 100 k pulldown. Refer to Table 2.
I/O SMBus-Compatible SDATA.
I _{SMBus-Compatible SCLOCK.}
2
Rev. 0.1