SI500S Datasheet, PDF (2/6 Pages) Silicon Laboratories – Quartz-free, MEMS-free, and pll-free all-silicon oscillator Any output frequencies from 0.9 to 200 MHz

Si500S
Parameters
Condition
Min
Typ
Max
Units
1.8 V option, 40 pF, 40 MHz, CMOS
—
13.9
16
mA
1.8 V option, 10 pF, 200 MHz, CMOS
—
16.7
19
mA
2.5 V option, 40 pF, 40 MHz, CMOS
—
15.8
18
mA
2.5 V option, 10 pF, 200 MHz, CMOS
—
19.3
22
mA
3.3 V option, 40 pF, 40 MHz, CMOS
—
17.7
20
mA
Supply Current
3.3 V option, 10 pF, 200 MHz, CMOS
—
SSTL-3.3, 200 MHz
—
21.5
24
mA
18.1
20.2
mA
SSTL-2.5, 200 MHz
—
18.0
19.7
mA
SSTL-1.8, 200 MHz
—
16.8
18.7
mA
Output Stopped, CMOS
—
11.8
13.1
mA
Tri-State
—
9.7
10.7
mA
Powerdown
—
1.0
1.9
mA
Output Symmetry
Rise and Fall Times³
0.5 x V_DD
46 – 13 ns/T_CLK
—
54 +
13 ns/T_CLK
%
CMOS, C_L = 15 pF measured from
20 to 80% of V_DD
—
1.4
2.0
ns
SSTL
—
—
0.6
ns
CMOS Output Voltage
SSTL-1.8 Output Voltage⁴
SSTL-2.5 Output Voltage⁴
SSTL-3.3 Output Voltage⁵
Powerup Time
V_OH, sourcing 9 mA
V_OL, sinking 9 mA
V_OH
V_OL
V_OH
V_OL
V_OH
V_OL
From time V_DD crosses min spec
supply
V_DD – 0.5
—
V_TT + 0.375
—
V_TT + 0.48
—
V_TT + 0.48
—
—
—
—
V
—
0.5
V
—
—
V
— V_TT – 0.375
—
—
V
—
V_TT – 0.48
—
—
V
—
V_TT – 0.48
—
2
ms
OE Deassertion to Clk Stop
Return from Output Driver
Stopped Mode
Return from Tri-State Time
Return from Powerdown Time
—
—
250 +
3 x T_CLK
ns
—
—
250 +
3 x T_CLK
ns
—
— 12 + 3 x T_CLK µs
—
—
2
ms
Period Jitter (1-sigma)
SSTL³
—
1
2
ps
RMS
Integrated Phase Jitter
1 MHz – 0.4 x F_OUT, SSTL or CMOS
and C_L < 7 pF,
—
F_OUT > 2.5 MHz
0.7
1.5
ps
RMS
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. V_TT = .5 x V_DD.
5. V_TT = .45 x V_DD.
2
Rev. 1.1