ISL6731A Datasheet, PDF (2/20 Pages) Intersil Corporation – Power Factor Correction Controllers

Pin Configuration
ISL6731A, ISL6731B
ISL6731A, ISL6731B
(14 LD SOIC)
TOP VIEW
NC 1
GND 2
ISEN 3
ICOMP 4
VIN 5
BO 6
OVP 7
14 GATE
13 NC
12 VCC
11 VREG
10 SKIP
9 FB
8 COMP
Pin Descriptions
PIN # I/O SYMBOL
DESCRIPTION
1, 13 -
NC Not Connected. Must be floating.
2
-
GND Ground pin. All voltage levels refer to this pin.
3
I
ISEN Current sense pin. The current through this pin is proportional to the inductor current.
4 I/O ICOMP Current error amplifier output pin.
5
I
VIN Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider
from the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the
input current. The phase lag is required to compensate the phase lead generated by the EMI filter.
6 I/O
BO This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will
follow the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor R_IS. The decoupling capacitor
provides ripple filtering. When the voltage at the BO pin (V_BO) drops below brownout voltage threshold, the controller
enters shutdown mode and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling
threshold.
7
I
OVP Overvoltage protection pin. Connect this pin to a resistor divider from the output. The resistor divider sets the OVP set point.
When the OVP pin voltage exceeds 104.5% of the reference voltage V_REF, OVP is triggered and the gate drive is disabled.
8 I/O COMP Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will
slowly ramp up the voltage of the COMP pin.
9
I
10 I/O
11
-
FB
SKIP
VREG
Voltage feedback pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage.
When the FB pin voltage exceeds 104% of V_REF, OVP is triggered and gate drive is disabled. When the FB pin drops below
10% of V_REF, the device is put into shutdown mode. There is an internal pull-down current source for open loop protection.
This pin has dual functions. Connecting this pin to ground disables the light load skip function. An internal 20μA current
sources out of this pin. Connect a resistor from this pin to the ground to set the average power trip point. The converter
exits the skip mode when either the VFB drops below 88% of V_REF, or the ISEN current goes above 29μA.
Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND
with a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.
12
I
VCC Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.
14 O
GATE
Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and
1.5A source capability.
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FN8582.1
February 13, 2015