AN113 Datasheet, PDF (19/52 Pages) Silicon Laboratories – SERIAL COMMUNICATION WITH THE SMBUS

AN113
;--------------------------------------------------------------------------------------
; SMBus ISR
;
; Implemented as a state table lookup, with the SMBus status register as the index.
; SMBus status codes are multiples of 8; thus the status code can be used to index
; program segments that are spaced by 8 bytes. Each ‘org’ command indicates
; a new state, offset from the beginning of the table by its status code value.
;
; Note that only 8 bytes are available to process each state. In the cases where
; more than 8 bytes are necessary, the code jumps to a program location outside
; of the state table. This is only necessary in the state ‘SMB_MTDBACK’.
SMBus_ISR:
push PSW
push ACC
push DPH
push DPL
push ACC
;
;
; Resource preservation
;
;
mov A, SMB0STA
; Load accumulator with current SMBus state.
; State corresponds to the address offset
; for each state execution
anl A, #7Fh
; Mask out upper bit, since any states that
; set this bit are not defined in this code.
mov DPTR, #SMB_STATE_TABLE
jmp @A+DPTR
; Point DPTR to the beginning of the state table
; Jump to the current state
; SMBus State Table------------------------------------------------------------------------
SMB_STATE_TABLE:
; SMB_BUS_ERROR
; All Modes: Bus Error
; Reset hardware by setting STOP bit
org SMB_STATE_TABLE + SMB_BUS_ERROR
setb STO
jmp SMB_ISR_END
; Jump to exit ISR
; SMB_START
; Master Transmitter/Receiver: START transmitted.
; The R/W bit will always be a zero (W) in this state because
; for both write and read, the memory address must first be written.
org SMB_STATE_TABLE + SMB_START
mov SMB0DAT, WRI_ADD
clr STA
jmp SMB_ISR_END
; Load slave address + W
; Manually clear START bit
; Jump to exit ISR
; SMB_RP_START
; Master Transmitter/Receiver: Repeated START transmitted.
; This state should only occur during a read, after the memory
; address has been sent and acknowledged.
org SMB_STATE_TABLE + SMB_RP_START
Rev. 1.3
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