SI4707-B20 Datasheet, PDF (16/30 Pages) Silicon Laboratories – WEATHER BAND AND SAME DATA RECEIVER

Si4707-B20
4.6. Tuning
4.8. Control Interface
The frequency synthesizer uses Silicon Laboratories’
proven technology, including a completely integrated
VCO. The frequency synthesizer generates the
quadrature local oscillator signal used to downconvert
the RF input to a low intermediate frequency. The VCO
frequency is locked to the reference clock and adjusted
with an AFC servo loop during reception. The tuning
frequency can be directly programmed using the
WB_TUNE_FREQ.
4.7. Reference Clock
The Si4707 reference clock is programmable,
supporting RCLK frequencies in Table 9. Refer to
Table 3, “DC Characteristics,” on page 5 for switching
voltage levels and Table 8, “WB Receiver
Characteristics¹,” on page 11 for frequency tolerance
information. Using RCLK is the recommended method
in order to meet the ±50 ppm requirement.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 12. This mode is enabled using the
POWER_UP command, see Table 11, “Si4707
Command Summary,” on page 19.
The Si4707 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4707 is performing the tune function, the
crystal oscillator may experience jitter, which may result
in lower SNR.
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4707 and
receive responses from the device. The serial port can
operate in three bus modes: 2-wire mode, 3-wire mode,
or SPI mode. The Si4707 selects the bus mode by
sampling the state of the GPO1 and GPO2 pins on the
rising edge of RST. The GPO1 pin includes an internal
pull-up resistor, which is connected while RST is low,
and the GPO2 pin includes an internal pull-down
resistor, which is connected while RST is low.
Therefore, it is only necessary for the user to actively
drive pins that differ from these states. See Table 10.
Table 10. Bus Mode Select on Rising Edge of
RST
Bus Mode
2-Wire
SPI
3-Wire
GPO1
1
1
0 (must drive)
GPO2
0
1 (must drive)
0
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins as
described in Section “4.9. GPO Outputs”. In any bus
mode, commands may only be sent after VIO and VDD
supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
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Rev. 0.8