EFR32BG12P232F Datasheet, PDF (16/181 Pages) Silicon Laboratories – EFR32BG12 Blue Gecko Bluetooth ®Low Energy SoC Family Data Sheet

EFR32BG12 Blue Gecko Bluetooth ^®Low Energy SoC Family Data Sheet
System Overview
3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.9.4 Capacitive Sense (CSEN)
The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches
and sliders. The CSEN module uses a charge ramping measurement technique, which provides robust sensing even in adverse condi-
tions including radiated noise and moisture. The module can be configured to take measurements on a single port pin or scan through
multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined ca-
pacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter,
as well as digital threshold comparators to reduce software overhead.
3.9.5 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with
several ranges consisting of various step sizes.
3.9.6 Digital to Analog Converter (VDAC)
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-
ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.9.7 Operational Amplifiers
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas. With
flexible built-in programming for gain and interconnection they can be configured to support multiple common opamp functions. All pins
are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to rail output. They can be used in
conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB space, and cost as compared with
standalone opamps because they are integrated on-chip.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32BG12. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 1024 kB flash program memory
• Up to 256 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
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