ISL6526-A Datasheet, PDF (12/18 Pages) Intersil Corporation – Operates from 3.3V to 5V Input

ISL6526, ISL6526A
100
f_Z1
f_Z2
f_P1 f_P2
OPEN LOOP
ERROR AMP GAIN
80
20 log



V^----V-_O^----I-_S^-N---_C^---_{}
60
40
COMPENSATION
GAIN
20
0
-20
20 log


RR_-----21_{--}
MODULATOR
-40
GAIN
f_LC
f_ESR
LOOP GAIN
-60
10
100
1k
10k 100k 1M 10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Charge Pump Capacitor Selection
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6526, ISL6526A when
operating the IC from 3.3V. Selecting the proper capacitance
value is important so that the bias current draw and the
current required by the MOSFET gates do not overburden
the capacitor. A conservative approach is presented in
Equation 10.
C_PUMP = ^I--^B----ⁱ-_V-^a---^s-_C--^A--_C--ⁿ---_^d----^G-_f--_s-^a----^t-^e--  1.5
(EQ. 10)
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equations 11 and 12:
I =
V_IN - V_OUT
f_s x L
x
V_OUT
V_IN
(EQ. 11)
V_OUT = I x ESR
(EQ. 12)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6526, ISL6526A will provide either 0% or 100% duty
cycle in response to a load transient. The response time is
the time required to slew the inductor current from an initial
current value to the transient current level. During this
interval, the difference between the inductor current and
the transient current level must be supplied by the output
capacitor. Minimizing the response time can minimize the
output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equations 13
and 14 give the approximate response time interval for
application and removal of a transient load:
t_RISE =
L x I_TRAN
V_IN - V_OUT
(EQ. 13)
t_FALL =
L x I_TRAN
V_OUT
(EQ. 14)
where: I_TRAN is the transient load current step, t_RISE is the
response time to the application of load, and t_FALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Submit Document Feedback 12
FN9055.12
September 30, 2015