SI5347-46 Datasheet, PDF (10/13 Pages) Silicon Laboratories – Data Sheet Errata for Product Revision B

8. Possible Part-per-Trillion Frequency Offset
Data Sheet Errata for Product Revision B
Possible Part-per-Trillion Frequency Offset
Description
Based on a device’s specific frequency plan and configuration, a minor frequency error may be generated in some output clock fre-
quency configurations. Refer to Si534x Applications Notification: Parts-per-Trillion Frequency Error for detailed information.
Impact
Affected frequency plans can result in output clocks’ frequency offsets between 1 and 10,000 part-per-trillion (ppt).
If the FINC/FDEC feature of the device is used to adjust the output frequency, the M divider is likely to use a value that triggers this
frequency offset issue. Since using FINC/FDEC causes the M values to change, there is no single frequency plan that will prevent this
from happening. Generally, applications that use FINC/FDEC are adjusting the frequency to match an external clock and the offset
caused by this error will be unnoticeable since the FINC/FDEC adjustments are orders of magnitude greater than the offset caused by
the error.
Workaround
ClockBuilder Pro configuration software enhancements address this issue. Download version v2.0 or later. After opening an existing
project file, ClockBuilder Pro will analyze the frequency plan for the frequency offset and re-calculate the entire frequency plan to use
the latest ClockBuilder Pro algorithms, while minimizing or eliminating the residual frequency offset issue.
Resolution
This erratum will be fixed in the next silicon revision; in the meantime, ClockBuilder Pro or later can be used to address this issue.
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