SI535 Datasheet, PDF (1/12 Pages) Silicon image – ULTRA LOW JITTER CRYSTAL OSCILLATOR (XO)

Si535/536
REVISION D
ULTRA LOW JITTER CRYSTAL OSCILLATOR (XO)
Features
 Available with select frequencies from  Available with LVPECL and
100 MHz to 312.5 MHz
LVDS outputs
 3^rd generation DSPLL^® with superior ^{ 3.3 and 2.5 V supply options}
jitter performance and high-power ^{ Industry-standard 5 x 7 mm}
supply noise rejection
package and pinout
 3x better frequency stability than ^{ Pb-free/RoHS-compliant}
SAW-based oscillators
Applications
 10/40/100G data centers
 10G Ethernet switches/routers
 Fibre channel/SAS/storage
 Enterprise servers
 Networking
 Telecommunications
Description
The Si535/536 XO utilizes Silicon Labs’ advanced DSPLL^® circuitry to
provide an ultra low jitter clock at high-speed differential frequencies. Unlike a
traditional XO, where a different crystal is required for each output frequency,
the Si535/536 uses one fixed crystal to provide a wide range of output
frequencies. This IC based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low jitter clocks in noisy environments typically found in
communication systems. The Si535/536 IC based XO is factory programmed
at time of shipment, thereby eliminating long lead times associated with
custom oscillators.
Functional Block Diagram
V_DD
CLK– CLK+
Fixed
Frequency
XO
100–312.5 MHz
DSPLL^®
Clock Synthesis
Si5602
Ordering Information:
See page 7.
Pin Assignments:
See page 6.
(Top View)
NC 1
6 VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si535
OE 1
6 VDD
NC 2
5 CLK–
GND 3
4 CLK+
Si536
OE
Rev. 1.1 6/15
GND
Copyright © 2015 by Silicon Laboratories
Si535/536