SI53314 Datasheet, PDF (1/32 Pages) Silicon Laboratories – 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53314
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ)
Features
 6 differential or 12 LVCMOS outputs  Independent V_DD and V_DDO:
 Ultra-low additive jitter: 45 fs rms
1.8/2.5/3.3 V
 Wide frequency range:
 1.2/1.5 V LVCMOS output support
dc to 1.25 GHz
 Excellent power supply noise
 Universal input with pin selectable
rejection (PSRR)
output formats
 LVPECL, Low Power LVPECL,
 Selectable LVCMOS drive strength to
tailor jitter and EMI performance
LVDS, CML, HCSL, LVCMOS
 Small size: 32-QFN (5x5 mm)
 2:1 mux with hot-swappable inputs _{ RoHS compliant, Pb-free}
 Individual output enable
 Industrial temperature range:
–40 to +85 °C
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Ordering Information:
See page 27.
Pin Assignments
Si53314
Description
The Si53314 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53314 features a 2:1 mux
making it ideal for redundant clocking applications. The Si53314 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz
with guaranteed low additive jitter, low skew, and low propagation delay variability.
The Si53314 features minimal cross-talk and provides superior supply noise
rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Functional Block Diagram
OE0 1
SFOUTA[1] 2
SFOUTA[0] 3
Q0 ⁴
Q0 5
GND 6
VDD 7
CLK_SEL 8
GND
PAD
Patents pending
24 OE5
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 VDDOB
18 VDDOA
17 VREF
VREF
Vref
Generator
VDD
Power
Supply
Filtering
VDDOA
SFOUTA[1:0]
OE[2:0]
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
Switching
Logic
BANK A
VDDOB
SFOUTB[1:0]
OE[5:3]
BANK B
Rev. 1.0 6/14
Copyright © 2014 by Silicon Laboratories
Si53314