SI3019-F-FSR Datasheet, PDF (1/128 Pages) Silicon Laboratories – PROGRAMMABLE VOICE DAA SOLUTIONS

Si3050+Si3011/18/19
PROGRAMMABLE VOICE DAA SOLUTIONS
Features
 PCM highway data interface
 µ-law/A-law companding
 SPI control interface
 GCI interface
 80 dB dynamic range TX/RX
 Line voltage monitor
 Loop current monitor
 +6 dBm or +3.2 dBm TX/RX level
mode
 Parallel handset detection
 3 µA on-hook line monitor current
 Overload detection
 Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
 TIP/RING polarity detection
 Integrated codec and 2- to 4-wire
analog hybrid
 Programmable digital hybrid for
near-end echo reduction
 Polarity reversal detection
 Programmable digital gain in 0.1 dB
increments
 Integrated ring detector
 Type I and II caller ID support
 Pulse dialing support
 3.3 V power supply
 Daisy-chaining for up to 16 devices
 Greater than 5000 V isolation
 Patented isolation technology
 Ground start and loop start support
 Available in Pb-free RoHS-compliant
packages
Applications
 DSL IADs
 VoIP gateways
 PBX and IP-PBX systems
 Voice mail systems
 DECT base stations
Description
The Si3050+Si3011/18/19 Voice DAA chipset provides a highly-programmable
and globally-compliant foreign exchange office (FXO) analog interface. The
solution implements Silicon Laboratories' patented isolation capacitor technology,
which eliminates the need for costly isolation transformers, relays, or
opto-isolators, while providing superior surge immunity for robust field
performance. The Voice DAA is available as a chipset, a system-side device
(Si3050) paired with a line-side device (Si3011/18/19). The Si3050 is available in
a 20-pin TSSOP or a 24-pin QFN. The Si3011/18/19 is available in a 16-pin
TSSOP, a 16-pin SOIC, or a 20-pin QFN and requires minimal external
components. The Si3050 interfaces directly to standard telephony PCM
interfaces.
Functional Block Diagram
Ordering Information
See page 106.
Package Options
Si3050
CS 1
FSYNC 2
PCKLK 3
DTX 4
DRX 5
RGDT 6
Si3050
Top View
GND
18 GND
17 VDD
16 VA
15 C1A
14 C2A
13 RESET
Si3011/18/19
CS
SCLK
SDI
SDO
SDI THRU
PCLK
DTX
DRX
FSYNC
RGDT
RG
TGD
TGDE
RESET
AOUT/INT
Si3050
Control
Data
Interface
Line
Data
Interface
Isolation
Interface
Control
Logic
Si3018/19
Isolation
Interface
Hybrid, AC
and DC
Terminations
Ring Detect
Off-Hook
RX
IB
SC
DCT
VREG
VREG2
DCT2
DCT3
RNG1
RNG2
QB
QE
QE2
NC 1 20 19 18 17 16
RX 2
15 DCT3
IB 3
C1B 4
IGND
PAD
14 QB
13 QE2
C2B 5
12 SC
6 7 8 9 10 11 NC
US Patent# 5,870,046
US Patent# 6,061,009
Rev. 1.5 10/11
Copyright © 2011 by Silicon Laboratories
Si3050 + Si3011/18/19