S-89713B Datasheet, PDF (7/23 Pages) Seiko Instruments Inc – MINI ANALOG SERIES LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER

MINI ANALOG SERIES LOW INPUT OFFSET VOLTAGE CMOS OPERATIONAL AMPLIFIER
Rev.1.0_00
S-89713B Series
„ Test Circuit (Per Circuit)
1. Power supply voltage rejection ratio, input offset voltage
R_S
R_S
R_F
V_DD
−
D.U.T
+
C_F
V_CMR = V_DD / 2
C_F
R_F
V_DDN
+
NULL
−
V_SSN
• Power supply voltage rejection ratio (PSRR)
The power supply voltage rejection ratio (PSRR) can be calculated
by the following expression, with V_OUT measured at each V_DD.
V_OUT
Test conditions:
When V_DD = 2.65 V: V_DD = V_DD1, V_OUT = V_OUT1,
When V_DD = 5.5 V: V_DD = V_DD2, V_OUT = V_OUT2
PSRR = 20 log


V_DD1 − V_DD2
^{VOUT1 − VD}2^D1 ^− ^{VOUT2 − VD}2^D2
× ^RF_R⁺_S^RS_{}

Figure 5
• Input offset voltage (V_IO)
^VOUT
−
V_{2DD}
×
R_S
R_F + R_S
2. Common-mode input signal rejection ratio, common-mode input voltage range
R_S
R_S
R_F
V_IN
V_DD
−
D₊.U.T
C_F
C_F
R_F
V_DDN
+
NULL
−
V_SSN
• Common-mode input signal rejection ratio (CMRR)
The common-mode input signal rejection ratio (CMRR) can be
calculated by the following expression, with V_OUT measured at each
V_IN.
V_OUT
Test conditions:
When V_IN = V_{CMR Max.}: V_IN = V_IN1, V_OUT = V_OUT1,
When V_IN = V_{CMR Min.}: V_IN = V_IN2, V_OUT = V_OUT2

CMRR = 20 log _

V_IN1 − V_IN2
(V_OUT1 − V_IN1) − (V_OUT2 − V_IN2)
× ^RF_R⁺_S^RS_{}
Figure 6
• Common-mode input voltage range (V_CMR)
The common-mode input voltage range is the range of V_IN in which
V_OUT satisfies the common-mode input signal rejection ratio
specifications.
Seiko Instruments Inc.
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