S-35399A02 Datasheet, PDF (42/55 Pages) Seiko Instruments Inc – 2-WIRE REAL-TIME CLOCK

2-WIRE REAL-TIME CLOCK
S-35399A02
Rev.1.0_00
„ Reset After Communication Interruption
In case of communication interruption in the S-35399A02, for example, during communication the power supply
voltage drops so that only the master device is reset; the S-35399A02 does not operate the next procedure because
the internal circuit keeps the state prior to interruption. The S-35399A02 does not have a reset pin so that users
usually reset its internal circuit by inputting a stop condition. However, if the SDA line is outputting “L” (during output of
acknowledgment signal or Read), the S-35399A02 does not accept a stop condition from the master device. In this
case, users are necessary to finish acknowledgment output or Read the SDA line. Figure 56 shows how to reset. First,
input a start condition from the master device (The S-35399A02 cannot detect a start condition because the SDA line
in the S-35399A02 is outputting “L”). Next, input a clock pulse equivalent to 1-byte data access (9-clock) from the SCL
line. During this, release the SDA line for the master device. By this procedure, SDA I/O before interruption is finished,
so that the SDA line in the S-35399A02 is released. After that, inputting a stop condition resets the internal circuit so
that restore the regular communication. This reset procedure is recommended to perform at initialization of the system
after rising the master device’s power supply voltage.
Start
condition
Clock equivalent to 1-byte data access
Stop
condition
SCL
1
2
8
9
SDA
(Output from
master device)
High-Z
SDA
(Output from
S-35399A02)
“L”
“L” or High-Z
High-Z
SDA
“L”
“L” or High-Z
High-Z
Figure 56 How to Reset
42
Seiko Instruments Inc.