S-93C46B Datasheet, PDF (21/45 Pages) Seiko Instruments Inc – CMOS SERIAL E2PROM

Rev.4.3_00
CMOS SERIAL E²PROM
S-93C46B/56B/66B
„ Function to Protect Against Write due to Erroneous Instruction Recognition
The S-93C46B/56B/66B provides a built-in clock pulse monitoring circuit which is used to prevent an
erroneous write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized
erroneously due to an erroneous clock count caused by the application of noise pulses or double counting
of clocks.
Instructions are cancelled if a clock pulse more or less than specified number decided by each write
operation (WRITE, ERASE, WRAL, or ERAL) is detected.
<Example> Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
Example of S-93C46B
CS
SK
Noise pulse
12345 6789
DI
Input EWDS instruction
100000000
Erroneous recognition as
ERASE instruction due to ^{1 1 10 0 0 00 0 0 0 0}
noise pulse
In products that do not include a clock pulse monitoring circuit, FFFF is
mistakenly written on address 00h. However the S-93C46B detects the overcount
and cancels the instruction without performing a write operation.
Figure 21 Example of Clock Pulse Monitoring Circuit Operation
Seiko Instruments Inc.
21