S-93C46B Datasheet, PDF (18/45 Pages) Seiko Instruments Inc – CMOS SERIAL E2PROM

CMOS SERIAL E²PROM
S-93C46B/56B/66B
Rev.4.3_00
4. 5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and
then input the ERAL instruction and an address following the start bit. Any address can be input.
There is no need to input data. The chips erase operation starts when CS goes low. If the clocks
more than the specified number have been input, the clock pulse monitoring circuit cancels the
ERAL instruction. For details of the clock pulse monitoring circuit, refer to “„ Function to Protect
Against Write due to Erroneous Instruction Recognition”.
CS
tCDS
SK
1 2 3 4 5 6 7 89
Verify
Standby
DI
<1> 0
010
DO
4Xs
tSV
tHZ1
Busy _Ready
Hi-Z
t PR
Figure 16 Chip Erase Timing (S-93C46B)
CS
tCDS
SK
1 2 3 4 5 6 7 8 9 10 11
Verify
Standby
DI
<1> 0
010
6Xs
DO
t SV
Busy _Ready
t PR
tHZ1
Hi-Z
Figure 17 Chip Erase Timing (S-93C56B, S-93C66B)
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Seiko Instruments Inc.