S-93C46B_1 Datasheet, PDF (20/50 Pages) Seiko Instruments Inc – 3-WIRE SERIAL E2PROM

3-WIRE SERIAL E²PROM
S-93C46B/56B/66B
Rev.7.0_00
„ Function to Protect Against Write due to Erroneous Instruction Recognition
The S-93C46B/56B/66B provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous
write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to
an erroneous clock count caused by the application of noise pulses or double counting of clocks.
Instructions are cancelled if a clock pulse more or less than specified number decided by each write operation
(WRITE, ERASE, WRAL, or ERAL) is detected.
<Example> Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
Example of S-93C46B
CS
SK
Noise pulse
12345 6789
DI
Input EWDS instruction
Erroneous recognition as
ERASE instruction due to
noise pulse
100000000
1 1 10 0 0 00 0 0 0 0
In products that do not include a clock pulse monitoring circuit, FFFF is mistakenly written
on address 00h. However the S-93C46B detects the overcount and cancels the instruction
without performing a write operation.
Figure 22 Example of Clock Pulse Monitoring Circuit Operation
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Seiko Instruments Inc.