S-93C46B_1 Datasheet, PDF (17/50 Pages) Seiko Instruments Inc – 3-WIRE SERIAL E2PROM

Rev.7.0_00
3-WIRE SERIAL E²PROM
S-93C46B/56B/66B
4. 5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then
input the ERAL instruction and an address following the start bit. Any address can be input. There is no
need to input data. The chips erase operation starts when CS goes low. If the clocks more than the
specified number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For
details of the clock pulse monitoring circuit, refer to “„ Function to Protect Against Write due to
Erroneous Instruction Recognition”.
CS
Verify
Standby
t_CDS
SK
1 2 3 4 5 6 7 89
DI
c
0
010
High-Z
DO
4Xs
t_SV
t_HZ1
busy _ready
High-Z
t_PR
Figure 17 Chip Erase Timing (S-93C46B)
CS
t_CDS
SK
1 2 3 4 5 6 7 8 9 10 11
Verify
Standby
DI
c
0
010
6Xs
High-Z
DO
t_SV
t_HZ1
busy _ready
High-Z
t_PR
Figure 18 Chip Erase Timing (S-93C56B, S-93C66B)
Seiko Instruments Inc.
17