S-812C_1 Datasheet, PDF (20/52 Pages) Seiko Instruments Inc – HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR

HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR
S-812C Series
Rev.4.0_00
„ Precautions
• Wiring patterns for the VIN, VOUT and GND pins should be designed so that the impedance is low. When
mounting an output capacitor between the VOUT and VSS pins (C_L) and a capacitor for stabilizing the
input between VIN and VSS pins (C_IN), the distance from the capacitors to these pins should be as short
as possible.
• Note that output voltage may be increased at low load current of less than 1 µA.
• At low load current less than 100 µA output voltage may increase when the regulating operation is halted
by the ON/OFF pin.
• To prevent oscillation, it is recommended to use the external parts under the following conditions.
Equivalent Series Resistance (ESR): 10 Ω or less (in case of using output capacitor)
Input series resistance (R_IN):
10 Ω or less
• A voltage regulator may oscillate when power source impedance is high and input capacitor is low or not
connected.
• Pay attention to the operating conditions for input/output voltage and load current so that the power loss in
the IC does not exceed the power dissipation of the package.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of
the products including this IC upon patents owned by a third party.
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Seiko Instruments Inc.