S-812C_1 Datasheet, PDF (16/52 Pages) Seiko Instruments Inc – HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR

HIGH OPERATING VOLTAGE CMOS VOLTAGE REGULATOR
S-812C Series
Rev.4.0_00
„ Operation
1. Basic Operation
Figure 16 shows the block diagram of the S-812C Series.
The error amplifier compares the reference voltage (V_ref) with V_fb, which is the output voltage resistance-
divided by feedback resistors R_s and R_f. It supplies the gate voltage necessary to maintain the constant
output voltage which is not influenced by the input voltage and temperature change, to the output
transistor.
VIN
Current supply
V_ref
Error amplifier
−
+
*1
VOUT
R_f
Reference
voltage
circuit
R_S
VSS
*1. Parasitic diode
Figure 16
2. Output Transistor
In the S-812C Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Be sure that V_OUT does not exceed V_IN + 0.3 V to prevent the voltage regulator from being damaged due
to inverse current which flows, because of a parasitic diode between the VIN and VOUT pin.
16
Seiko Instruments Inc.