S-1711 Datasheet, PDF (20/44 Pages) Seiko Instruments Inc – SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION

SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1711 Series
Rev.3.1_01
 Standard Circuit
Input
C_IN^*1
VIN
VOUT1
ON/OFF1 _VOUT2
ON/OFF2
VSS
C_L2^*2
Output 1
Output 2
C_L1^*2
Single GND
GND
*1. C_IN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 1.0 μF or more can be used for C_L1 and C_L2.
Caution
Figure 21
The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
 Condition of Application
Input capacitor (CIN):
Output capacitor (CL1, CL2):
ESR of output capacitor:
1.0 μF or more
1.0 μF or more
1.0 Ω or less
Caution Generally a series regulator may cause oscillation, depending on the selection of external parts.
Confirm that no oscillation occurs in the application for which the above capacitors are used.
Use input/output capacitor which has good temperature characteristics (conforming to the ceramic
capacitor EIA X5R (JIS B) characteristics).
 Selection of Input and Output Capacitors (CIN, CL1, CL2)
The S-1711 Series requires an output capacitor between the VOUT and VSS pins for phase compensation. Operation is
stabilized by a ceramic capacitor with an output capacitance of 1.0 μF or more in the entire temperature range. When
using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must be 1.0 μF or
more, and the ESR must be 1.0 Ω or less.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor. The required capacitance of the input capacitor differs depending on the application.
The recommended capacitance for an application is CIN ≥ 1.0 μF, CL1 ≥ 1.0 μF, CL2 ≥ 1.0 μF; however, when selecting
the output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual
device.
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