S-8233A Datasheet, PDF (19/30 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK

Rev.3.2_10
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Battery Protection IC Connection Example
FET-A
FET-B
EB+
R6
1 MΩ
R5
10 KΩ
Battery 1
R11
C1
R1
Battery 2
R12
C2
R2
Battery 3
R13
C3
R3
FET1
DOP
VCC
CD1
COP
Nch open
drain
FET2
VC1
CD2
S-8233A series
FET3
VC2
CD3
VSS
VMP
CTL
R7 1 KΩ
GND: Normal operation
Floating: Inhibit charging
and discharging.
CCT
C4
Over charge delay
time setting
Over discharge delay
time setting
CDT
C5
FET-C
COVT
C6
High: Inhibit over
discharge
detection.
Over current delay
time setting
EB-
Figure 9
[Description of Figure 9]
R11, R12, and R13 are used to adjust the battery conditioning current. The conditioning current
during over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To
disable the conditioning function, open CD1, CD2, and CD3.
The over charge detection delay time (t_CU1 to t_CU3), over discharge detection delay time (t_DD1 to t_DD3),
and over current detection delay time (t_IOV1) are changed with external capacitors (C4 to C6). See
the electrical characteristics.
R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a
100 kΩ to 1 MΩ resistor.
R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ
resistor.
If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters
the over current mode. C6 must be connected to prevent it.
If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of
battery voltage when the over current occurs. In this case, a charger must be connected to return
to the normal condition. To prevent this, connect an at least 0.01 µF capacitor to C5.
If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and
VSS, the delay time increases and an error occurs. The leak current must be 100 nA or less.
Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 µA or
less. If over discharge is inhibited by using this FET, the current consumption does not fall below
0.1 µA even when the battery voltage drops and the IC enters the over discharge detection mode.
R1, R2, and R3 must be 1 kΩ or less.
R7 is the protection of the CTL when the CTL terminal voltage higher than V_CC voltage. Connect a
300 Ω to 5 kΩ resister. If the CTL terminal voltage never greater than the V_CC voltage (ex. R7
connect to V_SS), without R7 resistance is allowed .
Seiko Instruments Inc.
19