S-8253A Datasheet, PDF (18/32 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK

BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.3.7_00
7. Delay Circuit
The following detection delay times are determined by dividing a clock of approximately 3.57 kHz by the counter.
(Example) Oscillator clock cycle (T_CLK) :
Overcharge detection delay time (t_CU) :
Overdischarge detection delay time (t_DL) :
Overcurrent detection delay time 1 (t_IOV1) :
Overcurrent detection delay time 2 (t_IOV2) :
280 µs
1.15 s
144 ms
9 ms
4.5 ms
Remark The overcurrent detection delay time 2 (t_IOV2) and overcurrent detection delay time 3 (t_IOV3) start when the
overcurrent detection voltage 1 (V_IOV1) is detected. As soon as the overcurrent detection voltage 2 (V_IOV2) or
overcurrent detection voltage 3 (V_IOV3) is detected over the detection delay time for overcurrent 2 (t_IOV2) or
overcurrent 3 (t_IOV3) after the detection of overcurrent 1 (V_IOV1), the S-8253A/B turns the discharging control
FET off within t_IOV2 or t_IOV3 of each detection.
V_DD
DOP pin voltage
V_SS
VMP pin voltage
V_DD
V_IOV1
V_IOV2
V_IOV3
V_SS
Overcurrent detection
delay time 2 (t_IOV2)
Figure 10
t_D
0 ≤ t_D ≤ t_IOV2
Time
Time
8. CTL Pin
The S-8253A/B Series has a control pin for charge / discharge control and shortening the test time. The levels, “L”, “H”,
and “M”, of the voltage input to the CTL pin determine the status of the S-8253A/B Series: normal operation, charge /
discharge inhibition, or test time shortening. The CTL pin takes precedence over the battery protection circuit. During
normal use, short the CTL pin and VSS pin.
Table 10 Conditions Set by CTL Pin
CTL Pin Potential
Status of IC
Open
Charge / discharge inhibited status
High (V_CTL ≥ V_CTLH)
Middle (V_CTLL < V_CTL < V_CTLH)
Charge / discharge inhibited status
Delay time-shortening status ^*1
Low (V_CTLL ≥ V_CTL)
Normal status
*1. In this status, delay times are shortened in 1 / 60 to 1 / 30 scale.
*2. The pin status is controlled by the voltage detection circuit.
COP Pin
High-Z
High-Z
(^*2)
(^*2)
DOP Pin
V_DD
V_DD
(^*2)
(^*2)
Caution 1. If the potential of the CTL pin is middle, overcurrent detection voltage 1 (V_IOV1) does not operate.
2. If you use the middle potential of the CTL pin, contact SII marketing department.
3. Please note unexpected behavior might occur when electrical potential difference between the
CTL pin (“L” level) and VSS is generated through the external filter (R_VSS and C_VSS) as a result of
input voltage fluctuations.
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Seiko Instruments Inc.