S-8253A Datasheet, PDF (16/32 Pages) Seiko Instruments Inc – BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK

BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.3.7_00
„ Operation
Remark Refer to “ „ Battery Protection IC Connection Example”.
1. Normal Status
When all of the battery voltages are in the range from V_DLn to V_CUn and the discharge current is lower than the specified
value (the VMP pin voltage is higher than V_DD − V_IOV1), the charging and discharging FETs are turned on.
Caution When the battery is connected for the first time, discharging may not be enabled. In this case, short
the VMP pin and VDD pin or connect the charger to restore the normal status.
2. Overcharge Status
When any one of the battery voltages becomes higher than V_CUn and the state continues for t_CU or longer, the COP pin
becomes high impedance. Because the COP pin is pulled up to the EB+ pin voltage by an external resistor, the
charging FET is turned off to stop charging. This is called the overcharge status. The overcharge status is released
when one of the following two conditions holds.
(1) All battery voltages become V_CLn or lower.
(2) All of the battery voltages are V_CUn or lower, and the VMP pin voltage is V_DD − V_IOV1 or lower (since the discharge
current flows through the body diode of the charging FET immediately after discharging is started when the
charger is removed and a load is connected, the VMP pin voltage momentarily decreases by approximately
0.6 V from the VDD pin voltage. The IC detects this voltage and releases the overcharging status).
3. Overdischarge Status
When any one of the battery voltages becomes lower than V_DLn and the state continues for t_DL or longer, the DOP pin
voltage becomes V_DD level, and the discharging FET is turned off to stop discharging. This is called the overdischarging
status. After discharging is stopped due to the overdischarge status, the S-8253A/B Series enters the power-down
status.
4. Power-down Status
When discharging has stopped due to the overdischarge status, the VMP pin is pulled down to the V_SS level by the R_VMS
resistor. When the VMP pin voltage is lower than Typ. 0.8 V, the S-8253A/B Series enters the power-down status. In
the power-down status, almost all the circuits of the S-8253A/B Series stop and the current consumption is I_PDN or lower.
The conditions of each output pin are as follows.
(1) COP pin : High-Z
(2) DOP pin : V_DD
The power-down status is released when the following condition holds.
(1) The VMP pin voltage is Typ. 0.8 V or higher.
The overdischarging status is released when the following two conditions hold.
(1) All battery voltage is released at V_DUn or higher when the VMP pin voltage is Typ. 0.8 V or higher and the VMP
pin voltage is lower than V_DD.
(2) All battery voltage is released at V_DLn or higher when the VMP pin voltage is Typ. 0.8 V or higher and the VMP pin
voltage is V_DD or higher (when a charger is connected and VMP pin voltage is V_DD or higher, overdischarge
hysteresis is released and electric discharge control FET is turned on at V_DLn).
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Seiko Instruments Inc.