S-13R1 Datasheet, PDF (18/49 Pages) Seiko Instruments Inc – REVERSE CURRENT PROTECTION CMOS VOLTAGE REGULATOR

REVERSE CURRENT PROTECTION CMOS VOLTAGE REGULATOR
S-13R1 Series
Rev.1.2_01
 Operation
1. Basic operation
Figure 18 shows the block diagram of the S-13R1 Series.
The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage
resistance-divided by feedback resistors (Rs, Rf). It supplies the gate voltage necessary to maintain the constant output
voltage which is not influenced by the input voltage and temperature change, to the output transistor.
VIN
Current
supply
V_ref
Error
amplifier
−
+
Reference voltage
circuit
*1
R_f
V_fb
R_s
VOUT
VSS
*1. Parasitic diode
Figure 18
2. Output transistor
In the S-13R1 Series, a low on-resistance P-channel MOS FET is used as the output transistor.
Since there exists a parasitic diode between the VIN pin and the VOUT pin, the reverse current arises when potential of
VOUT becomes higher than VIN. However, the reverse current detection circuit prevents the current from flowing from
the VOUT pin in the S-13R1 Series. Therefore, the IC is not damaged even when the potential of VOUT becomes higher
than VIN.
18