S-13R1 Datasheet, PDF (15/49 Pages) Seiko Instruments Inc – REVERSE CURRENT PROTECTION CMOS VOLTAGE REGULATOR

Rev.1.2_01
REVERSE CURRENT PROTECTION CMOS VOLTAGE REGULATOR
S-13R1 Series
 Standard Circuit
Input
C_IN^*1
VIN
VOUT
ON / OFF
VSS
Output
C_L^*2
Single GND
GND
*1. CIN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 1.0 μF or more can be used as CL.
Figure 16
Caution The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
 Condition of Application
Input capacitor (CIN):
Output capacitor (CL):
1.0 μF or more
1.0 μF or more
Caution Generally a series regulator may cause oscillation, depending on the selection of external parts.
Confirm that no oscillation occurs in the application for which the above capacitors are used.
 Selection of Input and Output Capacitors (CIN, CL)
The S-13R1 Series requires an output capacitor between the VOUT pin and the VSS pin for phase compensation.
Operation is stabilized by a ceramic capacitor with an output capacitance of 1.0 μF or more over the entire temperature
range. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must
be 1.0 μF or more.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor. The required capacitance of the input capacitor differs depending on the application.
The recommended capacitance for an application is CIN ≥ 1.0 μF, CL ≥ 1.0 μF; however, when selecting the output
capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual device.
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