S-93C86B Datasheet, PDF (16/34 Pages) Seiko Instruments Inc – CMOS SERIAL E2PROM

CMOS SERIAL E²PROM
S-93C86B
Rev.2.2_00
„ Function to Protect Against Write due to Erroneous Instruction Recognition
The S-93C86B provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write
operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due
to an erroneous clock count caused by the application of noise pulses or double counting of clocks.
Instructions are cancelled if a clock pulse whose count other than the one specified for each write
instruction (WRITE, ERASE, WRAL, or ERAL) is detected.
<Example> Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
Example of S-93C86B
Noise pulse
CS
1 2 3 4 5 6 7 8 9 10 11 12 13
SK
DI
Input EWDS instruction
1000000000000
Erroneous recognition as
ERASE instruction due to
noise pulse
11 10 0 0 00
0000
00
00
In products that do not incorporate a clock pulse monitoring circuit, FFFF is
mistakenly written to address 00h. However the S-93C86B detects the over count
and cancels the instruction without performing a write operation.
Figure 12 Example of Clock Pulse Monitoring Circuit Operation
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Seiko Instruments Inc.