S1200 Datasheet, PDF(14/37 Page) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT LOW INPUT-AND-OUTPUT CAPACITANCE CMOS VOLTAGE REGULATOR

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S1200 Datasheet, PDF (14/37 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT LOW INPUT-AND-OUTPUT CAPACITANCE CMOS VOLTAGE REGULATOR

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HIGH RIPPLE-REJECTION LOW DROPOUT LOW INPUT-AND-OUTPUT CAPACITANCE CMOS VOLTAGE REGULATOR

S-1200 Series

Rev.5.1_01

ï® Operation

1. Basic operation

Figure 13 shows the block diagram of the S-1200 Series.

The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output

voltage resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to

maintain the constant output voltage which is not influenced by the input voltage and temperature

change, to the output transistor.

VIN

Current

supply

Vref

Error

amplifier

Reference voltage

circuit

Vfb

VOUT

VSS

*1. Parasitic diode

Figure 13

2. Output transistor

In the S-1200 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due

to reverse current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential

of VOUT became higher than VIN.

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