S-T111 Datasheet, PDF (13/23 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR

HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.2.1_00
S-T111 Series
„ Precautions
• Wiring patterns for the VIN, VOUT and GND pins should be designed so that the impedance is low.
When mounting an output capacitor between the VOUT and VSS pins (C_L) and a capacitor for stabilizing
the input between VIN and VSS pins (C_IN), the distance from the capacitors to these pins should be as
short as possible.
• Note that the output voltage may increase when a series regulator is used at low load current (1.0 mA or
less).
• Generally a series regulator may cause oscillation, depending on the selection of external parts. The
following conditions are recommended for this IC. However, be sure to perform sufficient evaluation
under the actual usage conditions for selection, including evaluation of temperature characteristics.
Input capacitor (C_IN):
1.0 μF or more
Output capacitor (C_L):
0.47 μF or more
Equivalent series resistance (ESR): 10 Ω or less
• The voltage regulator may oscillate when the impedance of the power supply is high and the input
capacitor is small or an input capacitor is not connected.
• The application conditions for the input voltage, output voltage, and load current should not exceed the
package power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
• In determining the output current, attention should be paid to the output current value specified in Table
4 in the “„ Electrical Characteristics” and footnote *5 of the table.
• SII claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
Seiko Instruments Inc.
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