S-L2980_1 Datasheet, PDF (13/23 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR

Rev.4.1_00
HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
S-L2980 Series
„ Precautions
• Wiring patterns for VIN pin, VOUT pin and GND pin should be designed to hold low impedance. When
mounting an output capacitor between the VOUT and VSS pins (C_L) and a capacitor for stabilizing the
input between VIN and VSS pins (C_IN), the distance from the capacitors to these pins should be as short
as possible.
• Note that output voltage may increase when a series regulator is used at low load current (1.0 mA or less).
• Generally a series regulator may cause oscillation, depending on the selection of external parts. The
following conditions are recommended for this IC. However, be sure to perform sufficient evaluation under
the actual usage conditions for selection, including evaluation of temperature characteristics.
Input capacitor (C_IN):
Output capacitor (C_L):
Equivalent Series Resistance (ESR):
Input series resistance (R_IN):
0.47 μF or more
1.0 μF or more^*1
10 Ω or less
10 Ω or less
*1. If the product whose output voltage will be is 1.7 V or less is used, the capacitance should be 2.2 μF
or more.
• A voltage regulator may oscillate when the impedance of the power supply is high and the input capacitor
is small or not connected.
• The application condition for input voltage, output voltage and load current should not exceed the package
power dissipation.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
• In determining output current attention should be paid to the output current value specified in the Table 4
for “„ Electrical Characteristics” and the footnote *5.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of
the products including this IC upon patents owned by a third party.
Seiko Instruments Inc.
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