S-L2980_1 Datasheet, PDF (11/23 Pages) Seiko Instruments Inc – HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR

Rev.4.1_00
HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
S-L2980 Series
„ Operation
1. Basic Operation
Figure 11 shows the block diagram of the S-L2980 Series.
The error amplifier compares the reference voltage (V_ref) with the V_fb, which is the output voltage
resistance-divided by the feedback resistors R_s and R_f. It supplies the output transistor with the gate
voltage necessary to ensure certain output voltage free of any fluctuations of input voltage and
temperature.
VIN
Current source
V_ref
Error
amplifier
–
+
*1
R_f
VOUT
Reference voltage circuit
V_fb
R_s
VSS
*1. Parasitic diode
Figure 11
2. Output Transistor
The S-L2980 Series uses a low on-resistance P-channel MOS FET as the output transistor.
Be sure that V_OUT does not exceed V_IN+0.3 V to prevent the voltage regulator from being broken due to
inverse current flowing from VOUT pin through a parasitic diode to VIN pin.
Seiko Instruments Inc.
11